September 3rd, 2010

Fault Isolation and Nanoprobing Capabilities Within a Single Tool     Multiprobe nanoprober chinese site link    Multiprobe nanoprober Japanese Link    


 
 

Development of Backside SCM Technique
for Advanced SOI Microprocessors

Live, online, Tuesday June 30th, 8-9am from Singapore

Monday June 29th, from 5-6pm U.S. California (check time in your area)

 
Presented by Vinod Narang, Team Lead FA Engineer MTS at AMD Device Analysis Lab, SG

Vinod presents the scanning capacitance microscopy (SCM) technique developed from backside of SOI devices to delineate site-specific implant related issues for advanced microprocessors. The challenges include sample preparation methodology to obtain a thin oxide layer of high quality, SCM parameters optimization and data interpretation. Also included in his presentation: optimization of plasma etching of buried oxide, followed by a new method of growing thin oxide using UV/ozone. Case studies are shown highlighting the capability of backside SCM technique.

 

Vinod Narang bio available here.

 

 
             Can’t make it to the Live, Online, Seminar? Check our Video Archive later for recorded sessions.