Vinod Narang

Vinod holds a Master’s degree in Advanced Materials with focus on Microelectronics from MIT-NUS Joint program. Author of 16 technical papers, he is now team lead of Silicon level failure analysis group at Device Analysis lab AMD, Singapore; working on Reliability Qualification, Customer Rejects and Silicon Bring Up issues of advanced Microprocessor products based on 65nm & 45nm technology nodes. Prior to joining AMD, Vinod worked with TECH Semiconductor, a DRAM wafer fab on product yield failure analysis for various process technologies from 180nm to 110nm.

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