March 11th, 2010

Fault Isolation and Nanoprobing Capabilities Within a Single Tool     Multiprobe nanoprober chinese site link    Multiprobe nanoprober Japanese Link    

webinar video archive


F.A.C.E.S. Webinar : Recorded live on September 8th, 2009
Advanced Deconstruction Methodology for Copper Wafers


Christian Hobert GLOBALFOUNDRIES

Christian Hobert, MTS Product Engineer at GLOBALFOUNDRIES, Dresden Campus

Christian Hobert, of GLOBALFOUNDRIES, is a graduate of Technische Universität Chemnitz. He has a Masters degree in Electrical Engineering and minored in Semiconductor Physics/Micro Electronics. Specializing in semiconductor failure analysis, he leads the FA team within the Yield Engineering Department at the Dresden Campus.

Description: A key method for yield learning is physical failure analysis. Defects being analyzed by PFA are often hidden beneath a multiple level metallization stack and can be hardly visualized from a bird’s eye view. In that situation deconstruction processes come into play enabling a controlled layer-by-layer removal. Copper metallization production processes, when introduced, brought new challenges to the PFA community, which needed to be solved. In this presentation, Christian Hobert, MTS Product Engineer at Globalfoundries, (formally AMD), discusses his findings on deprocessing entire copper wafers instead of single dies to increase PFA productivity.

 


Access recording



F.A.C.E.S. Webinar : Pre-recorded
MultiProbe CAD package demo and training video


MultiProbe_CAD navigation

NEW: The MultiProbe Complete CAD Package
Reader and viewer in one system, presented by the developer


Description: A demo and training video for existing and prospective customers to use to hone skills, train staff, or simply see how the NEW complete CAD solution works in conjunction with the AFP tool.

The new MultiProbe CAD package release is a viewer and reader that is compatible with GDS files. It facilitates FA analysis by aligning device CAD overlays with the appropriate cells, giving engineers the precise location of where to probe and the ability to probe directly from the CAD overlay. The presentation takes you step by step through the system and offers a rare opportunity to learn from the software developer as he guides you through setup and navigation, and offers tips on how to achieve the best alignment when driving the AFP stage to the area of interest.

 

By invitation only. If you are interested in viewing this video, please contact susie@multiprobe.com
Please type VIEW CADNav into the subject line.

 



F.A.C.E.S. Webinar : Recorded live on June 30th, 2009 (from Singapore)
Development of Backside SCM Technique for Advanced SOI Microprocessors


Terry Kane

Vinod Narang, Team Lead FA Engineer MTS at AMD Device Analysis Lab, Singapore

Vinod has authored 16 technical papers, and holds a Master’s degree in Advanced Materials with focus on Microelectronics from MIT-NUS Joint program. He currently works on Reliability Qualification, Customer Rejects and Silicon Bring Up issues of advanced Microprocessor products based on 65nm & 45nm technology nodes. Prior to joining AMD, Vinod worked with TECH Semiconductor, a DRAM wafer fab on product yield failure analysis for various process technologies from 180nm to 110nm.

Description: Vinod presents the scanning capacitance microscopy (SCM) technique developed from backside of SOI devices to delineate site-specific implant related issues for advanced microprocessors. Included in this presentation: sample preparation methodology to obtain a thin oxide layer of high quality, SCM parameters optimization and data interpretation. Also included: optimization of plasma etching of buried oxide, followed by a new method of growing thin oxide using UV/ozone. Case studies are shown highlighting the capability of backside SCM technique.

 


Access recording



F.A.C.E.S. Webinar : Recorded live on January 28th, 2009
Calibration of Nanoprobe Capacitance-Voltage Spectroscopy (NCVS)


Terry Kane

Terry Kane, Senior Engineer in the IBM Semiconductor Research Design Center, East Fishkill, NY

Terry is responsible for electrical and physical characterization of 45nm, 32nm and 22nm node technologies at IBM's Semiconductor Research Design Center in East Fishkill, New York. A graduate of University of California, Berkeley, Terence has published over 35 technical papers and is member of IEEE and EDFAS. He is also a holder of more than 26 patents and was awarded a Supplemental Patent Award for the best patent in 2008.


Andy Erickson

Andy Erickson, Founder and President of MultiProbe

Go to Andy's bio

 

Andy Erickson is the founder and president of MultiProbe™ and the developer of the SCM sensor described in this presentation.

Description: Terry and Andy join forces in this Webinar to describe nanoprobe CV measurements of a discrete finger device from a multiple finger test structure. They show comparable results, obtained at the probe pad level, using an improved version of the earlier capacitance sensor. Finally, by comparing the BEOL test structure measurements with NCVS results from a single finger, they will verify and calibrate the nanoprobing technique.

 

play movie
Access recording



F.A.C.E.S. Webinar : Recorded live on November 15th, 2008
Atomic Force Probe Analysis of Non-Visible Defects in Sub-100nm CMOS Technologies

 

Randy Mulder

Randal Mulder, Freescale Semiconductor, Inc., Austin Texas

Mr. Mulder is a Senior Failure Analyst at Freescale's Quality Product Analysis Laboratory in Austin, Texas. He received his Bachelor of Science degrees in physics and electrical engineering from South Dakota State University, Brookings, S.D., and his Masters degree in electrical engineering from National Technological University, Minneapolis, Minn. He has 18 years of experience in the semiconductor industry in microelectronic failure analysis. Mr. Mulder has participated in several ISFTA paper review committees and has authored nine publications on semiconductor device failure analysis since 2003.

 

Description: Randall Mulder presents his findings on how Atomic Force Probing was used to characterize failing sub-100nm transistors, identify possible failure mechanisms and allow device/process engineers to make adjustments to the wafer fabrication process to correct the problem, even though physical analysis with SEM/TEM was not able to image and identify a failure mechanism.

 

 

play video

Access recording